Simulation and Implementation of Advanced Adder and Hybrid Multiplier for FIR Filter

Reduced power consumption and optimized area are given top priority in the development and application of digital signal processing (DSP) technology. The Filter of finite impulse response (FIR) is an essential part of this process because it maximizes area, speed, and power usage. Adder blocks, flip flops, and multiplier blocks make up the FIR filter. But the multiplier is usually the slowest block, which affects performance as a whole. In order to minimize power consumption and maximize multiplier speed, a hybrid multiplication technique is utilized. This method uses a hybrid adder (carry select, Weinberger, and Ling adder) to simultaneously add the partial products of two successive bits (multiplicands). Xilinx ISE 12.1 is used to synthesize and simulate the suggested design utilizing a variety of field programmable gate array (FPGA) devices.