Timing Characterization of a Semiconductor Random‐Access Memory

The timing characteristics define the templates of the times of all signals. Three standardization offices or professional associations have standardized the times specific to memory. These are the International Electrotechnical Commission, the Institute of Electrical and Electronics Engineers (IEEE) and the Joint Electron Device Engineering Council (JEDEC). This chapter gives the decoding keys of a timing diagram describing the operation of a semiconductor random-access memory. A timing diagram makes it possible to graphically represent the evolution of a logic signal over time. The chapter summarizes the different standardized states of a timing diagram. A state change is marked by a slash indicating the physical variation of the amplitude of the electrical signal. Manufacturers follow either the JEDEC standard, the IEEE standard or their own conventions. The two essential times are the access time and the cycle time. The chapter gives some numerical values of the characteristic times. They are lower and/or upper bounded.