Asymmetric Contact Engineering for Bottleneck‐Free Transport in 2D MoS 2 Field‐Effect Transistor

ABSTRACT Efficient carrier transport is a key requirement for designing high‐performance field‐effect transistor (FET) based on 2D transition metal dichalcogenides (TMDs). However, the unique structural characteristics of 2D semiconductors, which differ fundamentally from conventional 3D semiconductor materials, necessitate device architectures that deviate from traditional design approaches. Here, we propose a Bottleneck‐free Asymmetric Transistor Architecture (BATA) specifically tailored for 2D structures. Through technology computer‐aided design (TCAD) simulations, we reveal that adopting an embedded‐channel configuration at the source region maximizes charge carrier injection, while implementing a side‐channel configuration at the drain effectively mitigates the carrier transport bottleneck. Guided by this structural insight, we fabricated MoS 2 ‐based BATA devices that achieved near‐ideal subthreshold swing (SS) of approximately 60 mV/dec and field‐effect mobilities exceeding 200 cm 2 /V‐s, thereby demonstrating structurally enabled performance improvements over conventional FET. Furthermore, experimental validation of drain‐architecture‐dependent carrier transport bottlenecks was performed using mid‐voltage measurements and a single‐source dual‐drain asymmetric contact configuration. Finally, large‐scale integration was demonstrated through a 100‐device MoS 2 BATA array fabricated on a 2‐inch HfO 2 /Si wafer, confirming the robustness and scalability of the architecture. The BATA establishes a foundation for advancing 2D semiconductor‐based FET from laboratory demonstrations toward practical, fab‐compatible technologies.