Drive‐Level Capacitance Profiling Analysis of Polarity‐Dependent Trap States in GeSeTe and GeTe for Selector‐Only Memory

ABSTRACT The von Neumann architecture faces fundamental limits in data throughput and energy efficiency due to the physical separation of memory and processing units. Storage class memory (SCM) addresses this bottleneck by bridging dynamic random access memory (DRAM) and NAND flash. Among SCM technologies, selector‐only memory (SOM) stands out for its structural simplicity, relying solely on the nonlinear characteristics of selector materials. In this study, GeTe and GeSeTe chalcogenide devices are compared to assess their suitability for SOM operation. GeSeTe exhibits reliable threshold switching and voltage‐shifting characteristics of SOM, whereas GeTe does not show such functionality under identical conditions. Poole–Frenkel and trap‐limited conduction analyses reveal that GeSeTe displays pronounced polarity‐dependent differences in trap depth and trap density, while GeTe shows negligible dependence. Drive‐level capacitance profiling (DLCP) further demonstrates that GeSeTe features polarity‐dependent trap distributions, with deep traps dominating under positive bias and shallow traps under negative bias. This asymmetric trap occupation enables SOM operation in GeSeTe, whereas GeTe lacks such differential behavior. These findings highlight the importance of trap modulation and field sensitivity in SOM devices and establish DLCP as a valuable complement to current‐based analyses for understanding SOM switching mechanisms.