Phase Noise‐Aware Adaptive Master–Slave Charge‐Pump Fast Locking Phase‐Locked Loops

ABSTRACT A fast‐locking, low‐jitter, and low‐power phase‐locked loop (PLL) adopting adaptive master–slave charge‐pump architecture for L‐band RF wireless communication is proposed. By designing a novel adaptive switched logic control (ASLC) circuit combined with an auxiliary charge‐pump set, the proposed PLL can effectively achieve adaptive acceleration compensation in phase locking benefited from the multipath charging effect while controlling the increase of unexpected phase noise and power dissipation. Transfer function estimation on MATLAB is performed for phase noise modeling to predict the output noise and RMS jitter in CPPLL. Based on SMIC 180 nm/1.8 V standard CMOS technology, Cadence‐based circuit design and performance simulation are performed. The results demonstrate that the locking time from startup to stable 1.137GHz frequency output is only 0.23 μs, the RMS jitter is as low as 266 fs with just 5.699 mW power consumption, and the overall FoM value can be as high as 243.9 dB. The proposed L ‐band doubled CPPLL can be effectively applied in RF wireless communication signal generation and frequency synthesis such as satellite down‐frequency receiving, optical signal modulation, and digital audio broadcast (T‐DAB).