A Design of 30 MS/s 70.39 dB SNDR, 12‐Bit Charge‐Sharing ADC for Ultrasonic Imaging Applications

ABSTRACT This paper presents a 12‐bit, high speed charge‐sharing analog‐to‐digital converter (ADC), targeting low area and low power in wide bandwidth integrated RF transceivers for ultrasound diagnostic medical devices. The ADC comprises charge sharing digital‐to‐analog converter (DAC) with unit array capacitors with low threshold voltage devices for small area and low on resistance respectively. The circuit uses sample and hold circuit based on bootstrapping to reduce the effect of third harmonic. The dynamic latch comparator with adaptive power control improves the power efficiency. Furthermore, the asynchronous SAR logic delay cells are digitally controlled to minimize the power consumed by the digital part. The ADC achieves an effective number of bits (ENOB) of 11.40 bits and signal to noise distortion ratio (SNDR) of 70.39 dB at the input frequency of 500 kHz. The designed ADC is implemented with a 0.13 μm CMOS process occupying an area of 1600 μm × 505 μm. The designed SAR ADC draws 0.8 mA current per channel at a sampling rate of 30 MSPS when operated at a 1.5 V power supply.