Using Boolean Algebra to Minimize the LUT Count for FPGA Implementation of BCD Adders

ABSTRACT In this paper, the binary coded decimal (BCD) adder is efficiently mapped to FPGA resources to minimize the LUT consumption for different bit‐widths. Every FPGA slice contains a fast carry chain block CARRY4 which is used to add two BCD digits along with an input carry. The decimal adjustment after the addition is efficiently mapped to LUT to minimize the overall LUT count. As a result, the proposed design can efficiently realize one‐digit BCD addition in a single FPGA slice. Given the trade‐off between LUT consumption and delay the proposed design definitely offers a better trade‐off than the existing competing designs. Further using Boolean algebra, the INIT values stored in LUT are optimized to contain minimum number of bits set to . For any ‐digit BCD addition, the proposed design saves up to LUTs. However, it exhibits slightly higher delay than the competing designs which varies with the number of digits to be added. The delay for one‐digit BCD addition using LUT‐based design is approximately 6.543 ns, while the proposed design exhibits a delay of 7.717 ns. Further for eight‐digit BCD addition, the best‐case delay is ns while the proposed design exhibits ns more delay. The area savings achieved by the proposed design definitely makes it an appropriate choice for smaller embedded systems, where often area is prioritized over delay.