Design of CMOS Memtranstor Emulators With Enhanced Frequency for Chaotic and Neuromorphic Circuits

ABSTRACT This paper presents two CMOS‐based memtranstor emulator architectures capable of accurately replicating the flux‐charge ( φ ‐ q ) relationship and pinched hysteresis loop (PHL) characteristics of an ideal memtranstor. Both designs employ a voltage differencing inverting buffered amplifier (VDIBA) along with two second generation current conveyors (CCIIs), an analog multiplier, and a few passive components to realize nonlinear charge‐flux coupling. The first topology offers a compact, hardware‐efficient design with tunable butterfly‐shaped PHLs, whereas the second design introduces an external control voltage that enables quadrant‐dependent operation and adjustable hysteresis slopes. The proposed emulators operate at a low supply voltage of ±0.9 V, exhibit an operating frequency range of 35–50 kHz, with an average power consumption of 12.65 mW. Further, the emulator operates reliably for low frequencies up to 3 kHz, by appropriately setting the values of passive components. The tunability of the proposed memtranstor design is demonstrated by adjusting the bias voltage, excitation frequency, and capacitance. To validate the practical feasibility of the proposed architecture, a full‐custom layout of the memtranstor emulator has been designed, occupying a silicon area of 12882.93 μm 2 (165.06 × 78.05 μm). The post‐layout results show close agreement with the pre‐layout simulations while preserving the distinct memtranstance states of the emulator. Furthermore, the robustness of both designs is verified through extensive process‐voltage‐temperature analyses, confirming stable and reliable performance under device mismatch and environmental variations. The proposed memtranstor emulator circuits have been designed and simulated using Cadence Virtuoso 180 nm gpdk CMOS technology framework. The practical utility of the proposed emulators is further validated through two applications namely a chaotic oscillator—exploiting their nonlinear dynamics and an artificial synapse circuit—demonstrating long‐term potentiation and depression for neuromorphic computing. In addition, the hardware implementation of the proposed memtranstor emulator and chaotic oscillator has been carried out, to experimentally verify the functionality of the design. All these results highlight the proposed VDIBA‐CCII‐based memtranstor emulators as compact, tunable, and energy‐efficient circuits for nonlinear, chaotic, and neuromorphic hardware systems.