Stimulus‐Gated Neuromorphic Watermarking With 2D Siloxene‐Based UV Synaptic Phototransistors for Next‐Generation IC Security

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Authors: Rajat Banerjee, Priyanka Rani, Samik Mallik, Riya Sadhukhan, Asima Pradhan, Sanjoy Dey, Madhuchanda Banerjee, Dipak Kumar Goswami
Cited by: 1
References: 46

Abstract

Counterfeiting of integrated circuits (ICs) and intellectual property (IP) infringement pose increasing threats to modern electronics. Hardware watermarking is a key technology for anti-counterfeiting and IP protection. However, existing algorithmic and memory-based watermarking schemes are static, lack activation-level security, are inflexible, and are restricted only to IP protection. Herein, a groundbreaking stimulus-gated neuromorphic watermarking strategy for hardware security is demonstrated using UV-triggered synaptic phototransistors based on two-dimensional (2D) siloxene nanosheets. By emulating biological synaptic behavior, a dynamic watermark is designed that can only be unlocked via application of UV light pulses possessing precisely defined parameters of intensity, pulse duration, and pulse interval, thereby providing multi-layered activation-dependent security. These parameters are retained as manufacturer secrets, eliminating chances of reverse engineering and duplication of the watermark onto fake ICs. A deterministic excitatory post-synaptic current (EPSC)-stimulus model is developed that quantitatively links the optical input to synaptic current evolution, enabling reproducible logic-state transitions. Additionally, the flexible transistor array architecture permits integration of the watermark into wearable electronics. This work establishes an experimentally validated neuromorphic-based security paradigm in the time domain with stimulus-gated concealment, providing a watermarking scheme that functions both as an ownership identifier and as a practical anti-counterfeiting primitive for next-generation secure electronics.

Fields of Study & Subjects

Advanced Memory and Neural Computing Physical Unclonable Functions (PUFs) and Hardware Security Ferroelectric and Negative Capacitance Devices

Publication details

Journal / source
Small
Publisher
Wiley
Volume
22
Issue
14
Pages
e09193–e09193
Publication date
14 January 2026
Language
EN