Verification of Generic VHDL Designs and Their Translation to Rocq

Lecture notes in computer science 2026

View at publisher
Authors: Ocan Sankur, Benoît Boyer, Florian Faissole
DOI: 10.1007/978-3-032-15700-3_14
Cited by: 0
References: 24

Fields of Study & Subjects

Formal Methods in Verification Logic programming and type systems Embedded Systems Design Techniques

Publication details

Journal / source
Lecture notes in computer science
Pages
287–308
Publication date
1 January 2026
Language
EN