A Low-Power 3-Gb/s PRBS Generator Using an Improved TSPC D-Type Flip-Flop in 0.18 µm CMOS Technology

Circuits Systems and Signal Processing 2026

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Authors: Jau‐Ji Jou, Po-Yen Wang, Wahyu Hidayat, Bo-Hong Liu, Chun-Liang Yang, Chih‐Lung Tseng

DOI: 10.1007/s00034-025-03482-2

Cited by: 0

References: 32

Fields of Study & Subjects

VLSI and Analog Circuit Testing Low-power high-performance VLSI design Advancements in PLL and VCO Technologies

References 32