Efficient Design of Approximate Multipliers using Leading One-Bit and Recursive Approaches for Fault Tolerance in CNN Accelerators

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Authors: E. Jagadeeswara Rao, Akurathi Gangadhar, Mamidipaka Hema, K. V. Ramana Rao, Jahed Khan
Cited by: 1
References: 44

Fields of Study & Subjects

Low-power high-performance VLSI design Ferroelectric and Negative Capacitance Devices Advanced Memory and Neural Computing

Publication details

Journal / source
Circuits Systems and Signal Processing
Publisher
Springer Science and Business Media LLC
Volume
45
Issue
9
Pages
7252–7274
Publication date
20 February 2026
Language
EN