Optimization of novel DPTL-PFD design for fast-settling PLL frequency synthesizer using Taguchi–ANOVA

Analog Integrated Circuits and Signal Processing 2026

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Authors: Archana Singhal, Jyoti Sharma, Dheeraj Singh Rajput, Dharmendar Boolchandani, Chinnamuthan Periasamy

DOI: 10.1007/s10470-025-02555-1

Cited by: 0

References: 48

Fields of Study & Subjects

Advancements in PLL and VCO Technologies Radio Frequency Integrated Circuit Design Low-power high-performance VLSI design

References 48