Examining and Mitigating Underspecification in Neural Network-based Wafer Defect Pattern Classification

In semiconductor manufacturing, accurately classifying wafer defect patterns is crucial for quality control and yield enhancement. Deep learning models have demonstrated strong performance in this task. However, a persistent challenge in the field is ensuring the generalizability of models across different operational settings. While overfitting has been widely addressed in the literature, a less recognized yet crucial issue is underspecification, where multiple models trained on the same dataset achieve similar performance during the training phase, but differ significantly in real-world deployment. In wafer defect pattern classification, underspecification arises due to the inability of standard machine learning training procedures to identify whether models have learned true defect characteristics or spurious correlations from training data. In this study, we first investigate the presence of underspecification in wafer defect pattern classification by systematically analyzing widely used deep-learning models through stratified and contrastive stress tests. To mitigate this issue, we propose an adaptive invariance loss (AIL) leveraging a set-to-set contrastive formulation to enhance model generalization by dynamically adjusting the weighting of the invariance loss during training. This approach enables the model to prioritize defect-relevant features while reducing its sensitivity to confounding factors, such as fabrication inconsistencies or noise artifacts. Our experimental results demonstrate that the proposed AIL achieves more robust classification performance across various baseline models by effectively addressing underspecification. In particular, under wafer map size-based stratification, AIL improves CNN average test accuracy from $$69.30\%$$ to $$82.04\%$$ . Under waferIndex-based evaluation, AIL again achieves the best performance, with CNN reaching $$87.63\%$$ .