A 67 dB-SNDR 1.6 GS/s fully passive SAR-assisted noise-shaping pipelined ADC with gain error shaping
Fields of Study & Subjects
Analog and Mixed-Signal Circuit Design
Radio Frequency Integrated Circuit Design
Advancements in PLL and VCO Technologies
Publication details
- Journal / source
- Science China Information Sciences
- Volume
- 69
- Issue
- 3
- Publication date
- 22 January 2026
- Language
- EN