Hardware acceleration of the LESS canonical form computation
Abstract
Abstract LESS is a round 2 candidate of the onramp digital signature competition currently being organized by NIST. Recent work related to LESS introduced the notion of canonical forms, which enable substantially reduced signature sizes at the cost of additional computation during signing and verification. In this work, we investigate a hardware implementation of this new canonical form computation. The proposed architecture implements all computations of the canonical form computation with support for all parameter sets in a single hardware unit. The implementation results provide insight into the cost of this operation in hardware and the impact on the overall performance of the signature scheme.
Fields of Study & Subjects
Cryptography and Data Security
Cryptography and Residue Arithmetic
Chaos-based Image/Signal Encryption
Publication details
- Journal / source
- Cryptography and Communications
- Volume
- 18
- Issue
- 5
- Pages
- 1569–1588
- Publication date
- 10 January 2026
- Language
- EN