A unified and resource-efficient polynomial multiplication architecture for fully homomorphic encryption

Fully Homomorphic Encryption (FHE) plays a critical role in privacy-preserving computation; however, its performance is still largely constrained by the high latency and substantial hardware overhead introduced by the Number Theoretic Transform (NTT) and Inverse Number Theoretic Transform (INTT) operations in polynomial multiplication. Although existing unified or reconfigurable NTT/INTT accelerators alleviate control complexity to some extent, they commonly suffer from excessive multiplier consumption, low hardware utilization, and limited scalability when supporting varying polynomial sizes and modulus bit-widths, which is particularly unfavorable for resource-constrained FPGA platforms. To address this challenge, we propose a high-performance, reconfigurable NTT/INTT accelerator that can flexibly adapt to different polynomial sizes, modulus widths, and numbers of processing units. The architecture incorporates a bit-reversal-free memory access scheme to eliminate read–write conflicts and leverages a shift-optimized Montgomery reduction technique, which significantly reduces multiplier and Digital Signal Processor(DSP) resource consumption while maintaining support for multiple parameter configurations. Experimental results on a Xilinx Zynq-7000 FPGA (XC7Z100FFG900-2) demonstrate that the proposed design achieves notable improvements in latency, throughput, and area efficiency over prior works, confirming its feasibility and strong potential for accelerating FHE in resource-constrained environments.