A 0.00024 mm2, 18.9fJ/conv-step CIC-reused charge-injection SAR ADC with segmented sampling capacitors for computing-in-memory

Abstract This paper presents an area-efficient two-stage charge-injection SAR (CI-SAR) ADC for computing-in-memory (CIM) applications. By using a novel capacitive voltage-division sampling technique and proposed capacitive- divider-based charge-injection cell (CIC) reuse structure, the layout area occupied by the charge injection array is greatly reduced by 93.4%. Through proposed cooperative of coarse quantization stage and fine quan- tization stage, the sampled CIM signals can be accurately quantized into a 7-bit digital output with high power efficiency. Furthermore, a segmented common-mode shifting (S-CMS) technique maintains a stable common- mode voltage, preserving linearity throughout the entire conversion process. Verified in a standard 28 nm CMOS process, propose ADC occupies a chip area of only 0.00024 mm2 . Operating at 1GS/s with a 1 V supply, it achieves 40.79 dB SNDR and 48.78 dB SFDR with a Walden figure of merit (FoM) of 18.9fJ/conv-step, demonstrating competitive area and power efficiency for medium-resolution CI-SAR ADCs.