Deriving exhaustive test suites for Timed Finite State Machines with output delays

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Authors: Evgenii Vinarskii, Natalia Kushik, Nina Vladimirovna Yevtushenko, Djamal Zeghlache
Cited by: 0
References: 23

Fields of Study & Subjects

Software Testing and Debugging Techniques Formal Methods in Verification VLSI and Analog Circuit Testing

Publication details

Journal / source
Journal of Systems and Software
Volume
244
Pages
113077–113077
Publication date
28 August 2026
Language
EN