Statically scheduled interconnect for neural network inter-layer accelerating
Abstract
With the scale up of neural network (NN) accelerators, it is crucial to maintain a high utilization rate by processing different layers of NNs in pipeline.Previous works exclusively adopt dynamic networks on chip (NoCs) to transmit data between data-dependent layers, which are not optimal for NN inter-layer acceleration.Considering the dataflow between the NN layers is priorly known, we designed a statically scheduled network to transmit data between data-independent layers in NNs.The statically scheduled network can be configured to support many-to-many communication between layers, which is the essential traffic pattern in inter-layer acceleration.We also proposed a gather-scatter pathfinding algorithm to avoid deadlock and developed a compiler to automate the mapping from the data dependency in neural networks to the configuration of the statically scheduled network.Evaluation demonstrates the statically scheduled network costs 7.8x less area, delivers 2.54x to 3.35x higher performance, and achieves 5.6x to 9.9x power saving for inter-layer acceleration, compared to previous works.
Fields of Study & Subjects
Interconnection Networks and Systems
VLSI and FPGA Design Techniques
Parallel Computing and Optimization Techniques
Publication details
- Journal / source
- Microelectronics Journal
- Volume
- 171
- Pages
- 107098–107098
- Publication date
- 7 February 2026
- Language
- EN