A 17.6-GHz CMOS wide-ramping-range cascaded-PLL-based FMCW generator with 156-MHz/ μ s chirp slope and 2-GHz bandwidth

This article presents a 17.6-GHz CMOS frequency-modulated continuous wave (FMCW) generator based on cascaded-PLL architecture with detailed design considerations at both the system and the circuit levels. A unified phase-noise and chirp-linearity co-optimization framework for cascaded PLLs is introduced for the simultaneous implementation of low-noise and fast-chirp operation. The design principles and implementation of key circuit blocks are thoroughly discussed, including the noise contributions of individual devices in the ALF, a high-speed charge pump with glitch suppression, and the distinct design considerations of the two VCOs. Finally, an in-depth analysis of the measured FM error and phase noise during chirping is presented, which clarifies the respective impacts of system nonlinearity and PLL phase noise on FM linearity in single-point modulation. Fabricated in 40-nm CMOS, the proposed FMCW generator demonstrates a maximum chirp slope of 156 MHz/ μ s with 515.2-kHz root-mean-square (RMS) frequency error (i.e., 0.025% of chirp bandwidth) for 2-GHz chirp bandwidth, while achieving a measured PN of -107 dBc/Hz at 1-MHz offset from the 17.6 GHz carrier.