A gate sensing charges change LDO with no off-chip capacitor, dual transient enhancement and high PSR structure

—This paper proposes a gate sensing charges change capless LDO. Dual transient enhancement is used, which includes two kinds of overshoot and undershoot suppression structures. They detect changes of the LDO output voltage and converts it into a current that charges or discharges the gate of the power transistor to regulate load current indirectly. High PSR and foldback over-current protection structure are also included. The proposed LDO has been designed using the Semiconductor Manufacturing International Corporation (SMIC) 55nm CMOS process. The simulation results show that when the load current increases or decreases 320mA at the edge time of 100ns, the undershoot and overshoot of Vout is about 21.73 mV and 17.91mV respectively; PSR at light-load is -121.42 dB@DC, -37.2 8dB@1M Hz and -17.9 dB@10M Hz, and PSR at heavy-load is -121.3 8dB@DC, -35.64 dB@1M Hz and -16.54 dB@10M Hz.