Sub-2nm negative capacitance FET SRAM architecture: Achieving 49.85× leakage power reduction and 66× performance enhancement

Micro and Nanostructures 2026

View at publisher

Authors: Surbhi Bharti, Ashwni Kumar

DOI: 10.1016/j.micrna.2026.208689

Cited by: 2

References: 61

Fields of Study & Subjects

Ferroelectric and Negative Capacitance Devices Low-power high-performance VLSI design Advancements in Semiconductor Devices and Circuit Design

References 61