From vulnerability to robustness: Radiation-hard isolation for BPR-enabled stacked nanosheet CFETs

The integration of Buried Power Rail (BPR) and Complementary FET (CFET) technologies is a promising way to improve power efficiency and circuit density in advanced logic devices. However, the radiation reliability of BPR-integrated logic and memory circuits remains insufficiently explored. For the first time, we provide a quantitative analysis of Single Event Effects (SEE) in BPR-integrated Si-CFET structures using semiconductor device- and circuit-level simulator. Simulation results show that the BPR structure increases the local electric field intensity by approximately 20.2 % compared to the conventional Front Power Rail (FPR), leading to extended charge collection paths and transient current densities up to 41.5 % higher under identical irradiation conditions. Moreover, mixed-mode simulations of SRAM latch circuits indicate that bit-flips can occur at Linear Energy Transfer (LET) levels as low as 1–2 MeV cm 2 /mg, indicating significant vulnerability under low-voltage operation. To address this, structural mitigation strategies—such as Buried Dielectric Isolation and Backside Contact—are proposed to increase the threshold LET margin to 34 MeV cm 2 /mg, representing a 17-fold improvement, without degrading device performance. These results offer critical design insights for enhancing radiation robustness in ultra-scaled logic and memory architectures using BPR integration.