Adiabatic logic-based lightweight cryptography: A Low-Vt charge-balanced symmetric pre-resolve approach for power analysis resistant PRESENT

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Authors: Anjana Jyothi Banu, A. Prathiba
Cited by: 0
References: 23

Abstract

• Novel discharge mechanism improves charge balancing thus significantly reducing data-dependent power variations. • Provides protection against implementation-level attacks. • Implementation of the lightweight PRESENT block cipher. • Metrics confirm reduced energy variation and improved power uniformity. • A dedicated dataset was prepared for Deep Learning evaluation. Power analysis attacks pose a significant threat to the security of cryptographic hardware, particularly in resource-constrained environments where lightweight ciphers are deployed. Secure adiabatic logic, with its energy-recovery capability and inherent resistance to Side-Channel Attacks (SCA), has emerged as a promising countermeasure against power analysis attacks. In this work, we present a novel Low-Vt MOSFET-based Charge Balancing Symmetric Pre-Resolve Adiabatic Logic (CBSPAL) design, tailored to enhance resistance against power analysis attacks. The integration of Low-Vt transistors enables a more effective discharge mechanism through leakage of residual charge from previous computations, thereby improving signal symmetry and charge equalization. This choice significantly reduces data-dependent variations in dynamic power, a critical leakage source in correlation- and deep learning-based SCAs. The proposed Low-Vt CBSPAL logic gates (Buffer/NOT, AND/NAND, XOR/XNOR) are used to construct a secure implementation of the PRESENT lightweight cipher. Security assessment, using both statistical (Normalized Energy Deviation, Normalized Standard Deviation) and Deep Learning-based (DL-SCA) techniques, demonstrates a marked reduction in power trace distinguishability. For interpretability, NED/NSD values below 1% are classified as excellent, 1-5% as moderate, and above 5% as weak, providing practical thresholds for assessing hiding capability. The proposed design achieves a reduction of approximately 86.5% in NSD and 10.6% in NED compared with standard CBSPAL, with most metrics falling in the excellent range. These results highlight the robustness of the proposed approach against modern SCAs, establishing Low-Vt CBSPAL as both power-efficient and secure hardware solution for cryptographic applications.

Fields of Study & Subjects

Cryptographic Implementations and Security Low-power high-performance VLSI design Physical Unclonable Functions (PUFs) and Hardware Security

Publication details

Journal / source
Results in Engineering
Volume
29
Pages
109450–109450
Publication date
4 February 2026
Language
EN