A hybrid component-based and NARX framework for harmonic modeling of residential valley-fill LED lamp

Read full text
Authors: Hasan A. Abdulmajeed Salbi, Kiss Peter
Cited by: 1
References: 39

Abstract

This paper presents a unified, non-intrusive harmonic modeling framework for a Type D valley-fill passive Power Factor Correction (pPFC) Light-Emitting Diodes (LED) lamp under non-ideal supply conditions. The proposed methodology combines a physics-based Component-Based Modeling (CBM) implemented in MATLAB/Simscape with a black-box data-driven Nonlinear Autoregressive with Exogenous Input (NARX) model, both trained and validated using identical terminal voltage-current measurements. Eight EMI front-end configurations, together with post-rectifier parameters, are identified through Multi-Stage Ant Colony Optimization (MSACO) and Harris Hawks Optimization (HHO). A novel Comprehensive Error Index ( C E I ) is introduced by aggregating six category scores related to waveform, conduction, harmonics, power, power factor, and non-active power. Under pure sinusoidal supply, capacitor-inclusive topologies proved essential, reducing C E I from 21.70% for the ( R only) case to 4.33-4.28% for the full EMI model and 5.36-4.82% for the Pi filter. The reduced Pi filter formulation was further validated under ten voltage conditions ( 0.9 P , 0.95 P , P , 1.05 P , 1.1 P , F 1 − F 5 ), yielding C E I values of approximately 15.38-46.15% while preserving conduction angle and peak behavior. The Black Box Modeling (BBM)-NARX branch, strengthened through a ten-fold rotating condition-wise validation protocol, achieved high predictive fidelity with open-loop R = 0.997 − 0.999 , closed-loop R = 0.962 − 0.996 , and C E I values of 13.54-35.23%. Overall, the proposed framework provides a topology-specific yet robust basis for physically interpretable and data-driven Power Quality (PQ) aware harmonic modeling.

Fields of Study & Subjects

Impact of Light on Environment and Health Building Energy and Comfort Optimization Embedded Systems and FPGA Design

Publication details

Journal / source
Results in Engineering
Publisher
Elsevier BV
Volume
30
Pages
110882–110882
Publication date
6 May 2026
Language
EN