Breaking the loss barrier in CCTO: sol–gel tin enables high permittivity with capacitor-grade loss tangent

• Low-temperature (≈1020 °C) sol–gel synthesis yields dense, fine-grained Sn-doped CCTO ceramics. • Sn incorporation enhances dielectric response via mixed-valence (Cu + /Cu 2+ , Ti 3+ /Ti 4+ ) tuning. • Optimized microstructure achieves ε′ ≈ (4–7) × 104 and tan δ ≈ 0.06 at 1 kHz, 30 °C. • Dielectric performance surpasses that of conventional solid-state and sol–gel counterparts. Sn-doped CaCu 3 Ti 4 O 12 (CCTO) ceramics were synthesized by a sol–gel polymerization route using tin (II) acetate and low-temperature sintering (1015–1020 °C) to overcome the long-standing trade-off between colossal permittivity and dielectric loss (tan δ). Unlike solid-state processing, the sol–gel method yields small-grained, densely packed microstructures that reinforce grain-boundary (GB) barriers within the internal-barrier-layer-capacitor (IBLC) framework. Cu/Ti K-edge XANES confirms Cu 2+ as the dominant species with only trace Cu + , while the Ti 3+ fraction increases with Sn incorporation, evidencing mixed-valence tuning that governs electron hopping and GB blocking. Electrical mapping reveals two regimes: an ultra-high-ε′/high-loss domain at the lower sintering limit, and an optimized-balance domain at slightly higher temperature, retaining high ε′ while driving tan δ toward capacitor-grade levels. Representative compositions deliver ε′ ≈ (4–7) × 104 with tan δ ≈ 0.06 at 1 kHz (RT) , alongside α ≈ 6–7 and E b ≈ (1–2) × 10 3 V.cm −1 . The results establish Sn incorporation through a reduced-temperature sol–gel route as a mechanistically grounded, low-thermal-budget strategy for achieving low-loss, high-ε′ CCTO ceramics suitable for MLCC-relevant applications.