Assessment of dual-oxide options for LDMOS transistors in FinFET technology

We present a comparison of three LDMOS transistor designs in ≃ 16 nm FinFET technology with different gate stack configurations: thick ITL oxide, thin ITL oxide, and a combination of both (dual ITL oxide thickness). We analyze by simulation how the gate oxide stack influences the main performance and time-zero degradation rate indicators. The simulations suggest that, for the same doping profile and gate length (L G ), the dual-oxide configuration has transition frequency (f T ) and on-resistance (R DS,on ) within ≈ 16% and 6% of those of thick and thin-oxide devices, respectively, while the maximum substrate and gate currents are ≈ 35% and 43% smaller than for a fully thin-oxide device, respectively. Consequently, the dual-oxide configuration enables L G scaling and improvements in f T and R DS,on while keeping degradation monitors under control. • TCAD evaluation of the ITL thickness impact on f T , R DS,on , V BD , I B and I G . • New dual-oxide(DO) configuration (thin(tO) on channel; thick(TO) on drift region). • DO shows degradation and performance metrics similar to TO and tO, respectively. • Performance improvement but slight degradation increase when shortening DO devices.