An integrated multi-scale structured heat sink for the efficient heat dissipation of two-phase immersion-cooled chips
Abstract
• Experimental investigation of two-phase immersion cooling for data center applications. • A multi-scale structured heat sink is developed to enhance cooling of high-power chips. • High-speed imaging reveals bubble dynamics and the mechanism behind boiling enhancement. • Integrated vapor chamber and enhanced heat sink design lowers peak temperature and thermal gradient. Two-phase immersion cooling (TPIC) is positioned to become a critical thermal management solution for next-generation high-power chips. However, maintaining temperature uniformity remains challenging, with case temperatures often exceeding 70 °C under high power loads. This study introduces an integrated multi-scale structured heat sink, incorporating a vapor chamber (VC) as a heat spreader, to replace conventional cooling solutions. Experimental results demonstrate that this hybrid design achieves superior thermal performance: at a power input of 600 W, the maximum case temperature remains stable below 65 °C, with system thermal resistance below 0.026 °C/W. High-speed visualization reveals enhanced boiling dynamics achieved through multiscale surface engineering. Micro/nano-structured coatings promote vapor nucleation, while macro-scale pin–fin arrays augment the heat transfer area. This synergistic design significantly improves temperature uniformity, reducing the maximum temperature difference across the chip by 75 % (from 14.3 °C to 3.8 °C). Compared to baseline, the proposed architecture lowers the mean temperature by 22.1 %, and reduces the average thermal resistance by 6.4 %. This work presents a viable strategy for efficient thermal management of kilowatt-class chips, supporting the advancement of next-generation high-power computing systems.
Fields of Study & Subjects
Heat Transfer and Boiling Studies
Heat Transfer and Optimization
Fluid Dynamics and Thin Films
Publication details
- Journal / source
- Thermal Science and Engineering Progress
- Publisher
- Elsevier BV
- Volume
- 70
- Pages
- 104495–104495
- Publication date
- 14 January 2026
- Language
- EN