On-chip SRAM macro with 0.45μW/Mbit-leakage data retention using simultaneous control of source-line and body-line biasing

Integration 2026 Open access

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Authors: Hyejin Jo, Jaesung Lee, Dai Yun, Jihwan Mun, Kyeong‐Sik Min

DOI: 10.1016/j.vlsi.2026.102698

Cited by: 0

References: 10

Fields of Study & Subjects

Low-power high-performance VLSI design Advancements in Semiconductor Devices and Circuit Design Analog and Mixed-Signal Circuit Design

References 10