Fast and cost-effective stacking construction of silicon circuits from standard layers

The fabrication of integrated circuits (ICs) has long followed standard micro/nanofabrication procedures. In parallel to its enormous success in mainstream electronics, rising needs are calling for alternative methodologies for fabricating application-specific and simpler circuits, such as biomedical and Internet of Things (IoT) devices, using less time-consuming, more cost-effective, and more accessible approaches. Printed electronics provide an effective alternative, yet low mobility has limited their performance. Here, we report that by stacking pre-fabricated layers, it is possible to realize Si-based circuits of high uniformity, stability, and reproducibility, with day-level fabrication time, affordable cost, and minimum lab requirements. The constitutional units—stacked Si transistors—exhibit high mobility (∼200 cm 2 V −1 s −1 ). When combined with other transferable materials such as layered compounds and freestanding oxides, stacking also provides opportunities to quickly, effectively, and sustainably integrate extended functionalities into these Si-based electronics.