Interfacial Engineering toward Ultralow Thermal Boundary Resistance at Metal–Semiconductor Contacts

As semiconductor devices continue to scale down, thermal boundary resistance (TBR) has emerged as a critical bottleneck for heat dissipation. While conventional studies focus on engineering interfaces between devices and their heat spreaders, heat transport across metal–semiconductor junctions remains largely unexplored. This challenge is particularly pronounced in GaN devices, where experimental observations reveal a severe heat concentration beneath gate contacts. To address this issue, we propose an interfacial engineering strategy by using an ultrathin interlayer, yielding record-low TBR values of 3.5–4.6 m 2 K GW –1 between diverse metals and GaN. The introduction of a 3 nm-thick Ti interlayer not only facilitates elastic phonon coupling through acoustic impedance matching and strong interfacial bonding, but also significantly enhances phonon transmission by suppressing the interfacial disorder. This work establishes a scalable and universal framework for thermal management solutions in next-generation electronic devices.