Ultralow P-Type Contact Resistance Enabled by Evaporated SnS Contacts

Two-dimensional (2D) semiconductors are promising candidates for continued complementary metal-oxide semiconductor (CMOS) scaling, yet scalable p-type contacts still lag behind despite substantial progress in n-type contact engineering (e.g., semimetals). Here, we present a semiconductor–semiconductor van der Waals (S–S vdW) contact strategy in which the low density of states and low-energy deposition of SnS effectively suppress metal-induced gap states and defect-induced gap states. As a result, SnS contacts exhibit minimal Fermi-level pinning and enable a negligible hole-injection barrier, which is unattainable using conventional high-work-function metals such as Pd or Pt. Furthermore, SnS-WSe 2 transistors demonstrate a high on–off ratio of >10 10, a contact resistance as low as 395 Ω μm, and an on-state current density of up to 1.11 mA μm –1 at V DS = −2 V with a 60 nm channel length. This work provides a practical and reliable pathway toward high-performance 2D p-FETs and scalable 2D CMOS integration.