Impact of Surface Treatment on Noise in PL Measurements of Silicon Vacancies in 4H-SiC Lateral PIN-Diodes

Silicon vacancies (V Si ) in 4H-SiC are promising candidates for quantum technologies due to their long spin coherence times and integrability into mature semiconductor platforms. However, conventional CMOS-compatible processing introduces significant photoluminescence noise from passivation layers and crystal damage, degrading color center coherence and excitation line widths. This work evaluates strategies to minimize background noise. Thermally grown oxides with nitrogen monoxide annealing provide excellent low-noise passivation and remain stable during subsequent 600 °C thermal treatments. Furthermore, combining reactive ion etching with atomic layer etching eliminates ion-induced surface damage. Into lateral PIN-diodes, used for stark shift and photoluminescent excitation line width tuning, a selectively etched optical window is integrated. These devices show ideal electrical properties, blocking up to 150 V with leakage current below 10 pA/μm, while significantly enhancing the V Si environment. Single emitters in these PIN-diodes show an increased signal-to-noise ratio of 15 for near-surface and 50 for deeper emitters on both c-plane and a-plane wafers.