Ferroelectric-Polarization-Modulated 2D Floating-Gate Memory Enabling a 106 On/Off Ratio under ±1 V Gate-Voltage Sweep

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Authors: Tianze Yu, Ce Li, Weili Zhen, Dongliang Yang, Z D Zhang, Huihan Li, Yuxia Li, Ruitong Bie, Mingyue Yuan, Linfeng Sun
Cited by: 1
References: 49

Abstract

Abstract Floating-gate transistors based on 2D materials have attracted great interest owing to their superior memory characteristics and high reliability. However, most reported devices still suffer from high operating voltages, limited multifunctionality, etc. Here, we proposed a ferroelectric-polarization-modulated floating-gate transistor (FMFGT) based on a CIPS/MLG/hBN/MoS2 van der Waals heterostructure. The switchable and stable ferroelectric polarization of CIPS effectively reduces the tunneling barrier, exhibiting an on/off ratio (>106) when the sweep voltage is reduced to 1 V. In addition, the FMFGT exhibits robust dynamic response under an ultrafast pulse (∼20 ns) and achieves a maximum on/off ratio exceeding 109. Furthermore, the device demonstrates controllable synaptic plasticity under diverse stimuli, facilitating the integration of multiple optoelectronic logic gates. This work provides new insights into the role of ferroelectric polarization in floating-gate devices and establishes a promising solution toward low-voltage, multifunctional memories in edge computing and artificial intelligence.

Fields of Study & Subjects

2D Materials and Applications Ferroelectric and Negative Capacitance Devices Advanced Memory and Neural Computing

Publication details

Journal / source
Nano Letters
Publisher
American Chemical Society (ACS)
Volume
26
Issue
23
Pages
7554–7563
Publication date
3 June 2026
Language
EN