Thermoelectric Properties of p- and n-Type Epitaxial Ge1− x Sn x ( x = 0−0.23) Layers at Room Temperature: Role of Microscopic Lattice Tilt in Thermal and Electrical Transport

Abstract Understanding phonon and carrier transport in Group-IV alloys is essential for developing high-performance thermoelectric materials compatible with Si-based integration. Herein, we report the growth of p- and n-type Ge1−xSnx epitaxial layers (x = 0−0.23) on (001)-oriented substrates (Si, Ge, GaAs, and InP) via low-temperature molecular beam epitaxy. Moreover, their thermoelectric properties were systematically characterized at room temperature. Thermal conductivity (κ) was significantly reduced via Sn alloying and by decreasing the lateral correlation length ( ), which reflects microscopic lattice tilts induced by strain relaxation. This reduction is attributed to enhanced phonon scattering at domain boundaries, as corroborated by a Boltzmann transport model incorporating alloy, Umklapp, and boundary-scattering mechanisms. κ decreased from 23.6 (x = 0) to 1.5 W m−1 K−1 (x = 0.23) and 4.8 to 1.4 W m−1 K−1 in Ge0.95Sn0.05, with decreasing from 49 to 2.2 nm. Electrical conductivity (σ) and the Seebeck coefficient (S) were evaluated using high-resistivity substrates, revealing that carrier transport was less sensitive to compared with thermal transport in p-type layers, whereas a strong -dependence appeared in n-type layers. High power factors (PF = S2σ) of 10 and 30 μW cm−1 K−2 were achieved at room temperature for p- and n-type Ge-rich Ge1−xSnx layers (x ≤ 0.05), respectively. Thus, domain-boundary engineering via lattice tilt control is an effective strategy to suppress κ while preserving favorable electrical transport, inducing high power density in on-chip thermoelectric generators.