Electrically Reconfigurable Floating Gate Optoelectronic Synaptic Pixels for In-sensor Convolutional Image Feature Extraction with Built-in Contrast Enhancement

Image feature extraction and enhancement are fundamental operations in real-time object detection using convolutional neural networks (CNNs). In conventional architectures, continuous data transfer between sensors, memory, and processing units leads to high energy consumption and latency. In-pixel computing using optoelectronic synaptic (OS) devices offers a promising solution by enabling sensing and computation within the same hardware. However, most OS studies remain primarily device-centric and lack circuit-level considerations necessary for scalable system integration. Here, we present a two-dimensional material-based floating-gate optoelectronic synapse (FG-OS) that integrates device innovation with circuit codesign for CMOS-compatible in-pixel computing. The FG-OS employs large-area monolayer molybdenum disulfide (MoS 2 ) as the photoactive channel and bilayer graphene as the floating gate, enabling high optical responsivity even under low-light conditions. The device exhibits a superlinear photoresponse that intrinsically enhances image contrast during sensing. Importantly, the device supports low-voltage, circuit-friendly analog conductance modulation through fully electrical programming, eliminating the need for optical potentiation and simplifying array implementation. The codesigned architecture encodes 4-bit light-intensity-dependent information (16 levels) with strong robustness against cycle-to-cycle and device-to-device variations. Furthermore, we demonstrate in-pixel convolutional operations, including edge detection, image sharpening, and Gaussian blurring. These results highlight the computational versatility of the FG-OS array and establish a scalable pathway toward in-sensor processing and single-layer CNN architectures for intelligent vision systems.