A novel observation of negative differential resistance in a standard CMOS transistor and its application to a compact frequency doubler

Negative differential resistance (NDR)—in which current decreases with increasing voltage—represents nonlinear behavior in nanoscale devices, offering unique opportunities to probe carrier dynamics and field–matter interactions beyond conventional monotonic responses. While NDR has become a recurring feature in devices based on emerging materials, its occurrence in standard complementary metal-oxide-semiconductor (CMOS) transistors has been exceedingly rare. Achieving NDR within a CMOS-compatible platform is highly desirable, as it enables compact nonlinear functionalities without the need for multi-device circuits or additional biasing networks. Here we report the first experimental demonstration of two distinct NDR mechanisms in fully depleted silicon-on-insulator (FDSOI) transistors fabricated using an industry-standard CMOS process. At the drain terminal, a previously unreported NDR regime emerges at high drain bias due to hot-carrier injection into the drain-side dielectric, where localized trapping perturbs the electric field and suppresses impact ionization. In the body terminal, by contrast, NDR arises from the interplay of gate-induced drain leakage and lateral-field-enhanced impact ionization, achieving an unprecedented peak-to-valley ratio of 2.37 × 104 at 1.0 V with exceptional stability. Building on these findings, we demonstrate that the steep, low-voltage body-terminal NDR directly enables a reconfigurable frequency doubler within a single transistor. By linking terminal-specific transport dynamics to device-level nonlinear functions, this work establishes both a new physical framework for understanding NDR in silicon transistors and a CMOS-compatible route to compact, energy-efficient nonlinear circuit elements.