Surface code scaling on heavy-hex superconducting quantum processors

Demonstrating subthreshold scaling of a surface-code quantum memory on hardware whose native connectivity does not match the code remains a central challenge. We address this on IBM heavy-hex superconducting processors by co-designing the code embedding and control: a depth-minimizing SWAP-based “fold-unfold” embedding that uses bridge ancillas, together with robust, gap-aware dynamical decoupling (DD). We show that anisotropic scaling from distance 3 to (dx = 3, dz = 5) and (dx = 5, dz = 3) improves protection of Z- and X-basis logical states, respectively, and a calibrated ~ 30% noise reduction would enable isotropic (5, 5)-versus-(3, 3) scaling on this heavy-hex layout. We show that DD suppresses coherent ZZ crosstalk and non-Markovian dephasing during idle gaps, eliminating spurious subthreshold claims. To quantify performance, we derive an entanglement fidelity metric which reveals that widely used single-parameter suppression-factor fits can mischaracterize code performance. Our results provide a path to robust subthreshold surface-code scaling through optimized DD on non-native architectures. Demonstrating subthreshold scaling, whereby increasing the code distance reduces logical error rates when physical errors are below threshold, remains a major challenge on hardware with non native connectivity. Here, the authors show directional subthreshold scaling of a surface code on a heavy hex superconducting processor using connectivity aware embedding and dynamical decoupling.