Design and simulation of a p-type dual interbridge treeFET with comprehensive DC, analog/RF, and linearity analysis for CMOS circuit applications

This work presents the design and circuit-level validation of a p-type Dual Interbridge Tree-shaped Field-Effect Transistor (DIB-TreeFET), targeting a sub-3-nm technology node. The proposed device employs dual interbridge (IB) channels connecting horizontally stacked nanosheets, forming a tree-type configuration that enhances electrostatic control, channel coupling, and reduces short-channel effects. Device-level simulations reveal that the integration of high-k spacers significantly improves device performance compared to an air spacer. Specifically, the DIB-TreeFET achieves a 38.9% enhancement in ON-current, a 15.1% reduction in subthreshold swing, and a 46.5% reduction in DIBL, and a high current switching current ratio of \(I_{\text {ON}}/I_{\text {OFF}} \approx 10^7\) . In addition, the transconductance improves by 75.4%, indicating superior analog/RF characteristics. These improvements primarily arise from the higher permittivity of HfO 2 , which increases the gate capacitance ( \(C_{\text {gg}}\) ) and strengthens the electrostatic coupling between the gate and channel. Beyond device-level analysis, a three-stage current-starved ring voltage-controlled oscillator (VCO) is implemented and simulated using the proposed DIB-TreeFET using Sentaurus mixed-mode simulations, achieving a wide frequency tuning range of 20.48 GHz with stable oscillation behaviour. These results highlight the potential of the DIB-TreeFET as a promising device–circuit co-design solution for future nanoscale CMOS and RF system-on-chip (SoC) applications.