Hybrid approximate multiplier architectures for low power DWT image compression

Approximate computing is a means for energy efficient computing by allowing some degree of arithmetic imprecision for error tolerant processing applications such as image compression. This work presents a high-efficiency image compression architecture which exploits the use of hybrid approximate multipliers in the discrete wavelet transform (DWT)-pipeline. The work presents four approximate variants which are realized using hybrid Wallace, Dadda and Baugh-Wooley multipliers which results in significant reduction in delay, power consumption and hardware resource usage. Approximation is only used in the least significant areas of the calculation, and exact calculations are used for the most significant calculation areas to maintain visual accuracy. Experimental results show great improvements with the fourth variant of the approximate DWT. The proposed design shows a PSNR of 35.9 dB, a SSIM of 0.94 and compression ratio of 1.9 when integrated to the wavelet-based compression scheme. There is little deviation between original and reconstructed images based on the error analysis. Hardware performance analysis in terms of area, power, and delay is performed by FPG synthesis targeting Artix-7 platform. Overall, the obtained results show that strategic use of approximation in selected computational stages allows energy-efficient wavelet-based image compression without noticeable loss in the perceptual quality.