Digital twin platform for accelerating optimization of oxide semiconductor transistors to overcome fundamental performance-reliability trade-off

Abstract Amorphous oxide semiconductor (AOS) transistors are promising candidates for nextgeneration logic and high-density memory technologies, particularly for back-end-of-line– compatible monolithic three-dimensional integration. However, their widespread adoption is limited by a persistent trade-off between device performance and long-term reliability, the optimization of which conventionally requires exhaustive exploration of high-dimensional material, process, and device parameter spaces. Here, we introduce a closed-loop digital twin framework that accelerates AOS transistor optimization by integrating device fabrication, electrical characterization, circuit simulation, surrogate modeling and Bayesian active learning. Gaussian process–based surrogate models are used to link low-level fabrication parameters to device- and application-level performance and reliability metrics, enabling data-efficient, multi-objective optimization across the technology stack. By actively prioritizing the most informative experiments, the framework achieves over 3x reduction in experimental effort compared with exhaustive search. We demonstrate the approach using top-gated IGZO transistors spanning 80 gate oxide process splits and extend the optimization beyond device metrics to application-aware DRAM performance. This digital twin paradigm provides a scalable pathway to systematically navigate performance–reliability trade-offs and accelerate the development of emerging semiconductor technologies.