Raised or recessed? Finding the optimal gate architecture for improving the static performance of graphene transistors
Abstract
, and device yield increases from 54.4% to 65.1%. Physical analysis, which includes spectroscopy and hysteresis measurements, indicates that these improvements are due to the proposed planarized gate architecture and reduction of interface defects. This study shows that direct statistical comparison studies of process conditions can help identify favorable process conditions to improve the manufacturability of graphene-based transistors.
Fields of Study & Subjects
Graphene research and applications
2D Materials and Applications
Advancements in Semiconductor Devices and Circuit Design
Publication details
- Journal / source
- Nanoscale Advances
- Publisher
- Royal Society of Chemistry (RSC)
- Volume
- 8
- Issue
- 7
- Pages
- 2271–2282
- Publication date
- 1 January 2026
- Language
- EN