Fast‐Locking Frequency‐Hopping PLL Using Dual‐Edge Low‐Duty‐Cycle PFD With Cycle Slip Suppression

The performance of conventional phase–frequency detectors (PFDs) is critically limited by dead‐zone and blind‐zone artifacts, which stem from the timing constraints of D flip‐flop (DFF) based architectures. These non‐idealities degrade phase‐detection resolution, induce cycle slip, and prolong the lock time of phase‐locked loops (PLLs). This paper introduces a dual‐edge low‐duty‐cycle PFD (DELD–PFD) that utilizes high‐speed feed‐through and output‐prediction logic flip‐flops to detect both rising and falling edges of the input clocks, thereby eliminating the dead and blind zones and enhancing phase resolution. The proposed architecture inherently generates low‐duty‐cycle output pulses, which reduces charge‐pump current mismatch and improves loop dynamics. Fabricated in a standard 55 nm CMOS technology, the post‐layout simulation results validate operation across 1 MHz–5.5 GHz. The DELD–PFD achieves a lock‐time reduction of 63% relative to a conventional PLL, consumes 74 µW at 5 GHz from a 1.2 V supply, and delivers a phase noise of –147 dBc/Hz at a 1 MHz offset. Comprehensive Monte Carlo and PVT (process, voltage, and temperature) simulations confirm robustness across variations, demonstrating the design’s suitability for high‐speed, low‐noise, frequency‐hopping PLL applications.