Memristor‐Based Logic Circuits: Gate Designs and Cycle‐To‐Cycle Reliability

The implementation of two‐terminal memristors could decrease the dependency on the transistors in logic circuits, enabling high‐density circuits and reducing power consumption due to the memristor’s smaller feature size and non‐volatility, respectively. We propose universal logic function designs based on experimentally acquired electrical characteristics of ZnO‐based memristor devices. A highly accurate fitting of set and reset curves is achieved by employing a Verilog model and using it to design primitive gates. OR, NOR, NAND and AND gates can be designed by simply tuning the memristor and pull‐up resistor while using a similar circuit configuration. Based on this facile configuration, more complex circuits, such as XOR and XNOR gates, as well as half‐adder and half‐subtractor combinational logic circuits, can be achieved. Monte Carlo analysis results show that the gates’ output could suffer from a high variation in filament geometry during the cycle‐to‐cycle switching process, where the variation of the width and height of the filament affects the output significantly, while all gates are tolerant to the variation of the distance between the defects that make up the filament. This work not only highlights the promising alternative design for reconfigurable logical integrated circuits but also addresses the limitations that need to be overcome to design subsystems.