Power‐ and Area‐Efficient Concurrent Time‐Domain WTA–LTA Circuits
Abstract
ABSTRACT The proposed winner‐take‐all‐loser‐take‐all (WTA–LTA) circuit identifies both the winner and the loser simultaneously using a shared delay line and is suitable for applications where both the winner and the loser are important. Due to the shared delay line between the WTA and LTA cells, power consumption and occupied area are significantly reduced. The power consumption per cell at a frequency of 2 MHz is 5°nW and the occupied area per cell is 41.43°µm 2 . Moreover, the precision of the circuit for three cells is 99.4% for WTA and 99.2% for LTA. The proposed time‐domain WTA‐LTA circuit has been post‐layout simulated in 65‐nm technology with a supply voltage of 0.5 V.
Fields of Study & Subjects
Low-power high-performance VLSI design
Advancements in PLL and VCO Technologies
Analog and Mixed-Signal Circuit Design
Publication details
- Journal / source
- Electronics Letters
- Publisher
- Institution of Engineering and Technology (IET)
- Volume
- 62
- Issue
- 1
- Publication date
- 1 January 2026
- Language
- EN