Design of linear feedback shift register with single event upset resistance

The rapid development of China's aerospace industry has rendered the radiation-hardened integrated circuit design critically importance, especially for spacecraft chips requiring protection against cosmic high-energy particle effects. As a fundamental component of built-in self-test (BIST) structures that ensure chip reliability, the radiation hardening of linear feedback shift register (LFSR) necessitates special attention. A comprehensive radiation-hardening methodology for LFSRs through systematic analysis of single-event upset (SEU) mechanisms is proposed. The present approach integrates four synergistic design strategies. Firstly, a radiation-hardened D-flip-flop architecture by using 12-transistor dual-interlocked storage cells (DICE) with bit-line separation technique is implemented. Secondly, at the layout level, radiation hardening capability is enhanced through the implementation of guard rings, sensitive node area minimization and increased spacing between complementary sensitive nodes. Thirdly, a novel power-on-reset (POR) circuit with SEU-immune characteristics is developed to address initialization vulnerabilities. Finally, for XOR gates executing linear operations, the present design integrating C-element with bit-line separation techniques to resist SEU effects. Experimental validation through a 7-stage LFSR demonstrates that the radiation-hardened structure achieves significant SEU immunity enhancement while maintaining operational stability in radiation environments.