Significant lowering of interface state density of deposited-SiO2/4H–SiC MOS devices by two-step O2/N2 annealing

This study demonstrates a sequential O2/N2 annealing strategy to lower the interface state density (Dit) of deposited-SiO2/4H–SiC MOS devices. The SiO2 dielectric layer is formed on SiC by atomic layer deposition and subjected to low pressure O2 annealing at a relatively low temperature (800 °C), followed by N2 annealing at a relatively high temperature (800–1200 °C). A remarkably low Dit, as low as that of a thermally oxidized interface with NO annealing, is achieved by optimizing the two step annealing conditions. Furthermore, based on the systematic analysis, the physics of Dit lowering is understood as that low pressure O2 annealing suppresses carbon-defect formation and eliminates interface defects generated in deposition by inducing one or two atomic layers of SiC oxidation, while N2 annealing minimizes suboxide by incorporating N at the interface. Although a similar Dit lowering effect on the deposited interface is achieved as that of NO on the oxidized interface, the physics of Dit lowering is completely different.