Modeling memristor-based neural networks with Manhattan update: Trade-offs in learning performance and energy consumption

We present a systematic study of memristor-based neural networks trained with the hardware-friendly Manhattan update rule, focusing on the trade-offs between learning performance and energy consumption. Using realistic models of potentiation/depression (P/D) curves, we evaluate the impact of nonlinearity (NLI), conductance range, and number of accessible levels on both a single perceptron and a multilayer perceptron (MLP) trained on the MNIST dataset. Our results show that SPs tolerate P/D nonlinearity up to NLI ≤ 10−2, while MLPs require stricter conditions of NLI ≤ 10−3 to preserve accuracy. Increasing the number of discrete conductance states improves convergence, effectively acting as a finer learning rate. We further propose a strategy where one memristor of each differential pair is fixed, reducing redundant memristor conductance updates. This approach lowers training energy by nearly 50% in MLP with little to no loss in accuracy. Our findings highlight the importance of device–algorithm co-design in enabling scalable, low-power neuromorphic hardware for edge artificial intelligence (AI) applications.