An electric characterization method for identifying the number and position of unintended defect dots formed in silicon quantum dot devices

We propose a simple and generic electrical characterization method to identify the number and position of quantum dots (QDs) and to distinguish between the designed and unintentionally formed defects in silicon QD devices. This method uses single-electron current mapping in relation to plunger and barrier gate voltages. The Coulomb oscillation lines exhibited in the mapping are slanted because of the capacitive coupling between the QDs and the barrier gate. The lines with different slopes originated from different QDs, which allowed us to count the number of QDs in the device. In addition, the slope value allowed the estimation of the QD position. The lines with the largest absolute slope values likely originate from the designed QD, whereas others originate from unintentionally formed QDs. This method facilitates the development of silicon qubits during the process and fabrication optimization stages.